1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system, and more particularly relates to a semiconductor device whose power voltage is variable and an information processing system including the same.
2. Description of the Related Art
In semiconductor devices such as DRAMs (Dynamic Random Access Memory), for standardization, a power voltage and the like is strictly determined by the standards. For example, in a DDR3 (Double Data Rate) SDRAM (Synchronous DRAM), the power voltage is defined to be 1.5 V (1 G bits DDR3 SDRAM (Document No. E1494E50 (Ver. 5.0)) <http://www.elpida.com/pdfs/E1494E50.pdf>).
In recent years, because the demand for a low power consumption has been very high, many attempts have been made to reduce the power voltage. However, when the power voltage is changed, a waveform of an output signal output from an output driver also changes. Due to this, transmission and reception of signals cannot be performed correctly. As a result, various adjustments need to be performed with respect to the output driver and an input receiver. Generally, it is designed that, when reducing the power voltage, a slew rate before reducing the power voltage is maintained as a slew rate of the output driver.